1. Field of the Invention
The invention relates to a memory cell configuration, in particular for a DRAM memory module with memory cells that have a trench capacitor and a selection transistor, the trench capacitor being at least partly introduced into a semiconductor material.
Memory modules, in particular, dynamic random access memories (DRAMs), contain one or more cell arrays having memory cells. The memory cells are disposed in a matrix of rows and columns in a cell array. A memory cell has a selection transistor and a capacitor. A word line forms a control terminal of the selection transistor. The selection transistor is connected to the capacitor by a first terminal and to a bit line by a second terminal. The word lines and the bit lines are disposed perpendicular to one another.
German Published, Non-Prosecuted Patent Application DE 100 27 912 A1, corresponding to U.S. Pat. No. 6,496,401 to Weis, discloses a memory cell configuration of the generic type in which the capacitors are embodied in the form of trench capacitors. Advancing miniaturization of the memory modules means that the distances between the capacitors and the distances between the voltage-carrying regions become smaller and smaller. Moreover, the charge capacitance of the capacitors decreases further, the charge capacitance of the capacitor already being lower than the charge capacitance of the bit line that can be connected to the capacitor. On account of the low charge stored in the capacitor and on account of the short distances between the signal and control lines, such as, e.g., the bit lines and the word lines, the problem of mutual signal influencing arises.
It is accordingly an object of the invention to provide a memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that allows a high density of trench capacitors and, moreover, has a reduced signal coupling between the signal and/or control lines.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a memory cell configuration, including a semiconductor material having active regions, word lines and bit lines, memory cells each having a trench capacitor and a selection transistor, the trench capacitor being at least partly introduced into the semiconductor material and being electrically conductively connected to a bit line through the selection transistor, each of the selection transistors of the memory cells having a control terminal formed by a word line and first and second terminal regions formed in an active region of the semiconductor material, the first terminal region being conductively connected to a respective one of the trench capacitors, the trench capacitors of the memory cells being disposed in rows, the active regions being disposed respectively between two of the trench capacitors of the memory cells, a connecting line electrically conductively connecting two second terminal regions of two of the selection transistors of adjacent ones of the rows to one another and forming a common terminal region for two of the trench capacitors of different rows, and a contact bit terminal being electrically conductively connected to the common terminal region and being electrically conductively connected to a bit line.
The memory cell configuration according to the invention has the advantage that the trench capacitors are at a short distance from one another and, nevertheless, two trench capacitors can, optionally, be electrically conductively connected to a bit line through a contact bit terminal. The capacitances of the bit lines are reduced as a result of the saving of contact bit terminals.
The configuration according to the invention makes it possible, despite the compact configuration, for two trench capacitors to be electrically conductively connected to a bit line through a contact bit terminal. This is possible by virtue of the fact that a contact bit terminal is electrically conductively connected to two trench capacitors of different rows. The electrical coupling between the word lines (control lines) and the contact bit terminals (signal lines) is reduced as a result of the saving of a contact bit terminal. This affords higher interference signal immunity for reading out the information from the memory cells.
In accordance with another feature of the invention, the trench capacitors are, preferably, disposed in a regular grid, a central trench capacitor in each case being surrounded by four adjacent trench capacitors, the centers of the four surrounding trench capacitors in each case preferably being at the same distance from the center of the central trench capacitor, making possible a dense and regular configuration of the trench capacitors. The dense configuration results in a lower area requirement, and the regular configuration means that the layout for the trench capacitors can be produced simply and cost-effectively.
In accordance with a further feature of the invention, the contact bit terminal is disposed between two nearest word lines. Disposed adjacent to a nearest word line there is in each case a further word line, which form the control terminals for the selection transistors of the trench capacitors that can be conductively connected to the contact bit terminal. A simple, symmetrical, and compact configuration of the word lines is made possible in this way.
In accordance with an added feature of the invention, the trench capacitors have an upwardly tapering cross-sectional form. Moreover, the contact bit terminal is at least partly disposed above a trench capacitor. Such a configuration additionally saves the surface area. As a result, the memory cell configuration can be fabricated cost-effectively.
In accordance with an additional feature of the invention, the second terminal region of a respective selection transistor of an adjacent one of the trench capacitors is at least partly disposed above the trench capacitor and the contact bit terminal is at least partly disposed above the trench capacitor and is electrically conductively connected to the second terminal region and to the bit line.
In accordance with yet another feature of the invention, the word lines are at least partly routed above the trench capacitors.
In accordance with yet a further feature of the invention, the word lines are routed parallel beside one another and above trench capacitors. A simple, symmetrical and space-saving structure is achieved in this way.
In accordance with yet an added feature of the invention, the connecting line is introduced into the semiconductor material in the form of a doped region.
In accordance with yet an additional feature of the invention, the connecting line is embodied in the form of a conductive layer applied to the semiconductor material.
In accordance with again another feature of the invention, the height of the conductive layer preferably lies in the range of approximately 10 to 50 nm. The small height affords a reduction of the signal influencing between word line and signal line.
In accordance with again a further feature of the invention, a trench capacitor has a center and is surrounded by four trench capacitors each having centers at the same distance from the center of the trench capacitor.
In accordance with again an added feature of the invention, the connecting line between the two second terminal regions of the two trench capacitors that can be connected to a common contact bit terminal is embodied in the form of a doped region introduced into the semiconductor material.
In accordance with again an additional feature of the invention, the memory cell configuration has crossed bit lines, a true and a complementary bit line of a bit line pair being disposed in crossed fashion and being routed to a common amplifier circuit. The crossed configuration of the bit lines results in a reduction of the signal influencing between the bit lines during the read-out of a charge of a memory cell.
In accordance with still another feature of the invention, there are provided amplifier circuits, the bit lines being true and complementary bit lines alternately disposed one beside the other, a true and a complementary bit line forming a bit line pair, the bit line pair being routed to one of the amplifier circuits, the bit lines of the bit line pair being disposed in transposed fashion.
In accordance with still a further feature of the invention, the trench capacitors of two of the rows disposed one beside the other are disposed offset with respect to one another.
In accordance with still an added feature of the invention, the contact bit terminal is disposed between two rows of the trench capacitors and the bit lines are disposed between the rows of the trench capacitors and parallel to the rows of trench capacitors.
In accordance with a concomitant feature of the invention, the contact bit terminal is disposed between two rows of the trench capacitors, and at least one of the bit lines and the true and complementary bit lines are disposed between the rows of the trench capacitors and parallel to the rows of trench capacitors.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.